可訂購(gòu)部件
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 訂購(gòu)代碼(12NC) | 封裝 | 從經(jīng)銷商處購(gòu)買 |
|---|---|---|---|---|
| 74LVC08APW | 74LVC08APW,118 | 935250040118 | SOT402-1 | 訂單產(chǎn)品 |
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Click here for more information74LVC08APW
Quad 2-input AND gate
The 74LVC08A is a quad 2-input AND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
Alternatives
Features and benefits
Overvoltage tolerant inputs to 5.5 V
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數(shù)類型
| 型號(hào) | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC08APW | 1.2?-?3.6 | TTL | ± 24 | 2.1 | 150 | 4 | low | -40~125 | 144 | 8.4 | 70 | TSSOP14 |
PCB Symbol, Footprint and 3D Model
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封裝
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC08APW | 74LVC08APW,118 (935250040118) |
Active | LVC08A LVC08A Standard Procedure Standard Procedure |
TSSOP14 (SOT402-1) |
SOT402-1 |
SSOP-TSSOP-VSO-WAVE
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SOT402-1_118 |
環(huán)境信息
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC08APW | 74LVC08APW,118 | 74LVC08APW |
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文檔 (12)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC08A | Quad 2-input AND gate | Data sheet | 2025-05-06 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN263 | Power considerations when using CMOS and BiCMOS logic devices | Application note | 2023-02-07 |
| SOT402-1 | 3D model for products with SOT402-1 package | Design support | 2023-02-02 |
| lvc08a | lvc08a IBIS model | IBIS model | 2013-04-08 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP14_SOT402-1_mk | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
| SOT402-1 | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body | Package information | 2023-11-07 |
| SOT402-1_118 | TSSOP14; Reel pack for SMD, 13"; Q1/T1 product orientation | Packing information | 2025-01-16 |
| 74LVC08APW_Nexperia_Product_Reliability | 74LVC08APW Nexperia Product Reliability | Quality document | 2025-03-20 |
| lvc | lvc Spice model | SPICE model | 2013-05-07 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
PCB Symbol, Footprint and 3D Model
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訂購(gòu)、定價(jià)與供貨
| 型號(hào) | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購(gòu)買 |
|---|---|---|---|---|---|---|
| 74LVC08APW | 74LVC08APW,118 | 935250040118 | Active | SOT402-1_118 | 2,500 |
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樣品
作為 Nexperia 的客戶，您可以通過我們的銷售機(jī)構(gòu)訂購(gòu)樣品。
如果您沒有 Nexperia 的直接賬戶，我們的全球和地區(qū)分銷商網(wǎng)絡(luò)可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷商列表。
How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.